The present invention relates to a peripheral circuit for use with a synchronous semiconductor memory device and, more particularly, to a column address buffering circuit.
A double data rate synchronous dynamic random access memory (DDR SDRAM), which is recently emerging as a very high speed memory device, is an SDRAM in which data or instructions are inputted or outputted in synchronization with falling edges and rising edges of a clock signal. For instance, it is possible to obtain data corresponding to a clock signal of 200 megahertz (MHz) using both the rising and falling edges of a 100 MHz clock signal.
Like a conventional SDRAM, the DDR SDRAM performs a column access operation by using an internal clock signal aligned to rising edges of an external clock signal. To execute the column access operation synchronized to the rising edges and the falling edges of the external clock signal, the DDR SDRAM should employ a 2-bit prefetch scheme in which an access operation for rising data and falling data is performed in one clock cycle.
For example, if a column address xe2x80x98(A2, A1, A0)=(0, 0, 0)xe2x80x99 is inputted when a burst length is 2 and a burst type is a sequential type, although, on the outside, it looks like data corresponding to addresses of (0, 0, 1), (0, 1, 0) and (0, 1, 1) are sequentially outputted, internally, access operations for the column addresses of (0, 0, 0) and (0, 0, 1) are simultaneously performed in one clock cycle and those for the column addresses of (0, 1, 0) and (0, 1, 1) are simultaneously executed in the next clock cycle.
Herein, the xe2x80x98burst lengthxe2x80x99 means a length of data continuously outputted from a clock synchronous memory device such as an SDRAM.
As described above, when the burst length is 2, two column addresses are internally processed as aligned to the external clock signal. Therefore, if a column address A1 is constant regardless of a least significant column address A0 having a logic low or a logic high state, the memory is merely required to internally process a most significant column address to the lower column address A1 regardless of the state of the least significant column address A0.
However, if a logic state of the column address A1 is differently generated according to the logic state of the least significant column address A0, internally, the column address A1 is processed differently according to the logic state of the least significant column address A0. For instance, if column addresses (A1, A0) are (0, 0), internal column addresses to be processed in a corresponding clock are (0, 0) and (0, 1). Further, if column addresses (A1, A0) are (1, 0), internal column addresses to be processed in the corresponding clock become (1, 0) and (1, 1). Therefore, in case the least significant column address A0 has a logic low state, its upper column address A1 is processed regardless of the logic state of the least significant column address A0.
However, if starting column addresses (A1, A0) are (0, 1) or (1, 1), column addresses to be simultaneously processed in a corresponding clock become (1, 0) and (0, 0) and the column address A1 should be internally inverted. That is, in case the least significant bit address A0 has a logic high state, an inverted column address of A1, which is generated through a separate process, should be used.
In general, for the 2-bit prefetch scheme, it is common to classify cells in a bank in a memory device into odd and even cells and to access the odd cells and the even cells separately. Therefore, the column address A1 of the odd cell is generated to have a logic state identical to that of an external input address signal while the column address A1 of the even cell is produced to have a logic state varying depending on a logic state of the least significant column address A0.
Referring to FIG. 1, a block diagram of a conventional column address buffering circuit is shown. The column address buffering circuit comprises a multiplicity of address buffers 10, 12, 14, a plurality of address latches 20, 22, 24 and a bit transition detecting unit 30 for detecting logic states of lower column addresses corresponding to a burst length and outputting address signals at1_od and at1_ev to access an odd cell and an even cell.
Referring to FIG. 2, a circuit diagram of the bit transition detecting unit 30 in FIG. 1 when the burst length is 2 is illustrated. The bit transition detecting unit 30 includes a control signal generating block 31 for producing control signals set and setb. The control signal generating block 31 includes a 3-input NAND gate NAND1 that receives an output signal at_col_0 of the address latch 20 (FIG. 1) and inverted signals of an input signal A generated according to the burst length and an input signal B produced according to a burst type (e.g., a sequential or an interleave type) and generates the control signal set and an inverter IN6 inverting the control signal set to thereby produce the inverted control signal setb.
The bit transition detecting unit 30 further includes an output block 32 for providing its following predecoder (not shown) with the address signals at1_od and at1_ev in response to the control signals set and setb. The output block 32 includes an inverter chain IN1 and IN2 for buffering the output signal at_col_1 of the address latch 20 to thereby output a column address signal at1_od for an odd cell. The output block 32 also includes two switching components MT1 and MT2 for selectively providing a following predecoder (not shown) with the output signal at_col_1 or an inverted signal of the output signal at_ col_1 as a column address signal at1_ev for an even cell in response to the control signals set and setb.
Hereinafter, the operation of the above column address buffering circuit will be described with reference to FIGS. 1 and 2.
First of all, the address buffers 10, 12, 14 receive and buffer a plurality of column addresses A0, A1, An, respectively, in response to an internal clock signal clkp4 and the address latches 20, 22, 24 receive signals out_0, out_1, out_n provided from the address buffers 10, 12, 14, respectively, and generate output signals at_col_0, at_col_1, at_col_n responsive to an enabled address strobe signal add_stb.
The bit transition detecting unit 30 is provided with the lower bit address signals, e.g., at_col_0 and at_col_1 when the burst length BL is 2, applicable to the burst length among the output signals at_col_0, at_col_1, at_col_n of the address latches 20, 22, 24, and determines whether or not inverting an upper bit address signal, e.g., A1 when BL is 2, according to a logic state of the lower bit address signal, e.g., A0 when BL is 2, thereby transferring output address signals at1_ev and at1_od to the following predecoder (not shown).
Referring to FIG. 3, there is provided an operational timing diagram of the address buffering circuit in FIG. 1. In FIG. 3, if column addresses A0 and A1 having the waveform of (a) and (b) are inputted, two signals out_0 and out_1 having the waveform of (d) and (e) are simultaneously generated in synchronization with a rising edge of an internally generated clock signal clkp4 having the waveform of (c).
Subsequently, if there is coupled an address strobe signal add_stb having the waveform of (f), which is a kind of internal clock control signals, the internal signals, e.g., at_col_2, at col_n, except the lower bit signals at_col_0 and at_col_1 corresponding to the burst length are generated in synchronization with the address strobe signal add_stb while the internal signals at1_ev and at1_od corresponding to the even cell and the odd cell, respectively, are outputted to have the waveform of (h) after being delayed for a certain delay time td by the bit transition detecting unit 30.
Meanwhile, an access time of data corresponding to the inputted column address is determined by the latest signal. Therefore, as described above, because the output address signals at1_ev and at1_od of the bit transition detecting unit 30 are generated in the end, the access time of the column addresses is decided by the generation time of the output address signals at1_ev and at_od.
In short, because the output address signals at1_ev and at1_od, which are a part of internal signals to be used in performing a column access operation after being provided to address predecoders, are delayed by the bit transition detecting unit 30 including two or more inverters. The internal address signals at1_ev and at1_od are generated as being delayed for the certain delay time after the address strobe signal add_stb is inputted. This results in the problem of delaying the column access time and, thus, substantially deteriorating the operational speed of the memory device.
In accordance with one aspect, the disclosed column address buffering apparatus may include a plurality of address buffers for receiving and buffering column address signals to thereby output buffered column address signals and a bit transition detecting unit for receiving lower bit address signals corresponding to a burst length among the buffered column address signals and for selectively outputting a most significant bit address signal among the lower bit address signals or an inverted signal of the most significant bit address signal according to logic states of the rest of the lower bit address signals. The disclosed apparatus may also include a first address latch for supplying corresponding following predecoders with an output signal of the bit transition detecting unit in response to an address strobe signal and a second address latch for receiving buffered address signals which do not correspond to the burst length among the buffered address signals and providing corresponding following predecoders with the received buffered address signals in response to the address strobe signal.
In accordance with the disclosed apparatus, there is provided a column address buffering circuit for use in memory devices such as a DDR DRAM for receiving column addresses and internally buffering the column addresses. In the buffering process, the buffering circuit may generate specific internal address signals having different paths according to a burst length before an address strobe signal is inputted thereto so as to synchronize the generation time of the specific internal address signals with those of other internal address signals. As a result, it is possible to steeply shorten the column access time by removing an unnecessary time delay. That is, the inventive column address buffering circuit is configured to position a bit transition detecting unit related to generating the specific internal address signals corresponding to an odd cell and an even cell in front of an address latch for generating internal address signals at the same time of the address strobe signal being coupled, so that the specific internal address signals can be produced when the other internal address signals are generated.